1. Technical Field
The present subject matter relates generally to voltage controlled oscillators. More particularly, the present subject matter relates to a cross coupled voltage controlled oscillator architecture.
2. Background Information
A voltage controlled oscillator (“VCO”) is an electrical circuit that produces an oscillatory output voltage. VCOs are used in a wide variety of analog and digital circuits. VCOs are commonly used in phase lock loop (“PLL”) and clock generator circuits and are frequently used in data communication equipment.
In at least one implementation, a VCO comprises multiple delay elements serially connected in a “ring.” That is, the output of each delay element feeds into the input of the next delay element in series and the output of the last delay elements loops back and feeds into the input of the first delay element. This configuration is also known as a “ring oscillator.”
The output of each delay element in a ring oscillator, not only is provided to the next delay element in series, but also comprises an output clock signal. The frequency of the clock signals are all generally the same within a ring oscillator, but the phase varies from clock signal to clock signal in the circuit.
A ring oscillator oscillates at a particular frequency that generally is inversely proportional to the number of delay elements comprising the ring. A ring oscillator that is based on single-ended signaling typically includes an odd number of delay elements greater than or equal to three. All else being equal, a three stage ring oscillator has a higher oscillation frequency than a five stage ring oscillator which, in turn has a higher oscillation frequency than a seven stage ring oscillator, and so on. For many applications, such as data communications, ring oscillators with higher oscillation frequencies are preferred over ring oscillators with lower oscillation frequencies. A three-stage ring oscillator produces three clock signals varying in phase by 120 degrees. A five-stage ring oscillator produces five clock signals varying in phase by 72 degrees, and so on.
The desire for fast speeds encourages a system designer toward ring oscillator implementations with only three stages. However, in some applications such as data communications, a three-stage ring oscillator is undesirable because the clock signals produced by a three stage ring oscillator are incompatible with the application. Data communications, for example, frequently use a four-phase clock scheme. That is, four clock signals are used all having the same frequency but having phases varying by 90 degrees from clock to clock. Thus, one clock has a phase of 0, while the other three clocks have relative phases of 90, 180 and 270 degrees. A three-stage ring oscillator is fast, which is desirable, but produces clocks having phases that vary by 120 degrees, which is not desirable for some applications. A solution to this problem is desirable.